1. Field
Aspects of the present disclosure relate generally to receivers, and more particularly, to offset calibration for low power and high performance receivers.
2. Background
A receiver may be used to receive a high-speed data signal over a channel (e.g., in a serializer/deserializer (SerDes) communication system). The receiver may split the received data signal among multiple data paths, where each data path comprises a sample latch (e.g., for sampling data from the data signal). Offset voltages at the sample latches may be high (e.g., due to component mismatches in the receiver) and the offset voltage for each sample latch may be different, which negatively impact performance of the receiver (e.g., cause closure of the data eye at the sample latches). Accordingly, it is desirable to cancel out the offset voltage at each sample latch to improve performance of the receiver.